1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit, and a manufacturing method therefor.
2. Description of the Related Art
In order to increase the reliability of the tunnel insulating film of a nonvolatile semiconductor memory device, i.e., each of nonvolatile memory cells, an oxynitride film is used as the tunnel insulating film.
Formation of a high-quality oxynitride film requires annealing in an oxygen atmosphere after an oxide film is nitrided. However, it is reported in “Yaegashi et al., IEDM Tech. Dig., pp. 341–344, 1999” that when annealing in the oxygen atmosphere after nitriding is carried out, an impurity, particularly, boron in a silicon substrate is abnormally diffused.
In general, ion implantation into a channel of a MOS transistor is executed before a gate oxide film is formed. Thereafter, the gate oxide film is produced, and a gate electrode is provided on it.
If nitriding of an oxide film and subsequent annealing in the oxygen atmosphere are performed in the step of forming the gate insulating film, anomalous diffusion of the implanted channel impurity will be caused.
On the other hand, demands have arisen for attaining a shallow channel impurity profile as well as a fine device structure of the MOS transistor. If anomalous diffusion of impurity ions occurs after channel ion implantation, the shallow channel impurity profile cannot be controlled, failing to reduce the fine device structure of the transistor.
In order to improve the controllability of the channel impurity profile of the channel, a device process of implanting ions via a gate polysilicon electrode after forming the oxide film and gate electrode of a MOS transistor is proposed in “Arai et al., IEDM Tech. Dig., pp. 775–778, 2000”. According to this process, after a gate oxide film and a first gate electrode film are formed, a trench is formed in a semiconductor substrate by STI (Shallow Trench Isolation), and an oxide film is filled in the trench. Thereafter, channel ion implantation is done via the first gate electrode film, and a second gate electrode film is deposited on the first gate electrode film.
However, a process of depositing the second gate electrode film after filling the oxide film in the trench by STI is becoming unavailable with the fine device structure.
In order to miniaturize the nonvolatile memory cell, a floating gate electrode and the end of an isolation region in the direction of channel width must be self-aligned. In a device in which the floating gate electrode of the nonvolatile memory cell and the end of the isolation region in the direction of channel width are self-aligned, the floating gate electrode must be produced before the isolation region is formed by STI. The floating gate electrode must be formed as thick as, e.g., 1,500 Å or more in order to ensure a sufficiently large surface area of an ONO insulating film interposed between the floating gate electrode and a control gate electrode.
For such thick floating gate electrode, even if the channel ion implantation is done after formation of the isolation region by STI as the prior art, ions must be implanted at an acceleration voltage enough to pass through the thick floating gate electrode made of polysilicon. It is difficult to control the channel impurity profile shallowly.
As described above, the shallow channel impurity profile must be obtained in addition to the fine device structure of the nonvolatile memory cell or MOS transistor. If impurity ions anomalously diffuse after the channel ion implantation, the channel impurity profile cannot be controlled shallowly, and the fine device structure of the MOS transistor cannot be attained.
In the case of the thick floating gate electrode of the memory cell, even if the channel ion implantation is done after formation of the isolation region by STI, like the prior art, ions must be implanted at an acceleration voltage enough to pass through the thick floating gate electrode of the polysilicon. It is then difficult to control the channel impurity profile shallowly.
As the memory cell integration degree increases, the isolation width decreases. In the prior art, the floating gate electrode of the memory cell is divided by a slit pattern on an isolation layer, and an interpoly insulating film and control gate electrode are formed between the divided electrodes. However, as the isolation layer becomes narrower, it becomes more difficult to form a slit pattern on the isolation layer. The floating gate electrode must be formed in self-alignment with the element active region (AA region).